1. Field of the Invention
The present invention relates to the field of electronics, and more particularly to the field of testing of electronic devices.
2. Description of the Related Art
Electronic devices have been fabricated from CMOS technology for many years. CMOS technology is made possible by the fabrication of p-channel field effect transistors (PFETS) and n-channel field effect transistors (NFETS) on a common substrate. CMOS devices have an enormous advantage over devices fabricated according to other technologies, in that CMOS devices generally consume very low DC power and very low AC power at low frequencies.
Many logic families fabricated of CMOS technologies have been described in the literature. Static CMOS logic, domino logic, and dynamic precharge logic have been described and have become well known in the field of electronics. However, a new family, known as the N-NARY logic family, has also been developed. N-NARY devices are disclosed in U.S. Pat. Nos. 6,069,497 and 6,118,304, both of which are incorporated by reference into this application.
N-NARY signals are quite different from binary signals. Binary signals typically implement each bit on a distinct wire (parallel bus), or each bit one-at-a-time over a common wire (serial bus). The N-NARY signals, in contrast, encode at least one bit, and in many cases more than one bit, over a group of wires. The group of wires collectively implements the N-NARY signal, which can contain one bit or more than one bit.
Of the wires in an N-NARY signal, however, at most one can have a high voltage. For example, in a xe2x80x9c1-of-4xe2x80x9d N-NARY signal, four wires are used to implement two bits of information, having collectively four states. In a first state, the first wire is xe2x80x9chot,xe2x80x9d meaning having a high voltage. In a second state, the second wire is xe2x80x9chot;xe2x80x9d in a third state, the third wire is xe2x80x9chot;xe2x80x9d and in a fourth state, the fourth wire is xe2x80x9chot.xe2x80x9d In contrast, to achieve four distinct states in binary logic, two wires are used.
The nature of the N-NARY logic family has presented certain challenges for testing. When a tester applies a test vector to an N-NARY logic device, the test vector should be legal and realizable within the xe2x80x9crulesxe2x80x9d of N-NARY logic, since testing how a device responds to stimuli that the device will never actually experience is inefficient and possibly useless. Moreover, applying test vectors that are not legal can have unpredictable results and might even damage the circuit under test, since the circuit likely was not designed to handle such signals. Unfortunately, testers have generally been designed to apply binary signals to circuits under test, and some binary signals are not legal N-NARY signals. In N-NARY logic, a signal is legal if the signal includes at least two wires, and no more than one of the wires may have a high logic level at any time.
Generally, N-NARY numbers are the most efficient stimuli for exposing faults in N-NARY circuits. N-NARY numbers can be represented by a collection of one or more N-NARY signals. Each N-NARY signal represents a xe2x80x9cdigitxe2x80x9d or portion of the number. For example, the number xe2x80x9cfifteenxe2x80x9d implemented in 1-of-4 N-NARY logic would require two N-NARY signals, one of which represents the higher-order 1-of-4 value (the two most significant bits worth of information) and the other of which represents the lower-order 1-of-4 value (the least two significant bits of information).
One way to iterate through all possible test vectors is to count the numbers from 1 to the highest number that may be implemented. For example, in binary, to iterate through all possible test vectors, it is possible to count the binary numbers. Counting the binary numbers from 1 to 2nxe2x88x921 in binary provides a value for each of n bits, and associating each of the bits with a wire of the test vector provides a logic level for the circuit under test. Similarly, in N-NARY, to iterate through all possible test vectors, it is possible to count the N-NARY numbers. Counting the N-NARY numbers from zero to N, however, provides a value for each of N wires of the test vector, and provides a logic level for the circuit under test.
In binary, iterating through all possible binary numbers from 1 to 2nxe2x88x921 may be accomplished through the use of an n-bit counter. An n-bit counter may be implemented by n one-bit flip-flops in sequence. However, such an n-bit counter merely iterates through all of the binary numbers from 1 to 2nxe2x88x921 in consecutive order. To iterate through all of the binary numbers from 1 to 2nxe2x88x921 in a non-consecutive order, other structures have been developed. One such structure is the linear finite state machine, or LFSM. LFSMs that have n cells generally have been used to produce all of the binary numbers from 1 to 2nxe2x88x921 in a non-consecutive order.
The binary numbers from 1 to 2nxe2x88x921 produced by well-known LFSMs have generally been satisfactory for testing binary logic devices. For example, a circuit under test is partitioned into various test points, and each wire in a test point is associated with a distinct bit of a test vector. This is the built-in self-test (BIST) approach described in the co-pending application xe2x80x9cMethod and Apparatus For Built-in Self-test of Logic Circuitry,xe2x80x9d U.S. patent application Ser. No. 09/191,813, filed Nov. 13, 1998, which is incorporated by reference into this application. This approach is not necessarily true for other BIST implementations, however. Conventional BIST just hooks each cell to a primary input without partitioning per se. Other approaches used by well-known LFSMs include the LFSM producing test vectors that fully test the logic under test by achieving every possible input state (this type of testing is generally called xe2x80x9cexhaustive testingxe2x80x9d). More typically, however, the LFSM only generates a subset of the 2nxe2x88x921 numbers because it takes too long to generate all of the possible numbers. Indeed, there is a whole sub-field of testing concerned with how to guarantee test coverage without testing exhaustively that is not within the scope of this disclosure.
The present invention comprises a number transformer that includes an encoder that converts binary numbers to N-NARY numbers. Within an N-NARY number, exactly one of the bits has a value of one and all of the remaining bits have a value of zero. According to some aspects, several N-NARY numbers are generated in response to a binary number. A set of encoding instance selectors defines a partitioning of the bits of the binary number and a range of bits within each partition. The encoder then converts each subset of bits of the binary number to a corresponding N-NARY number, such that exactly one of the bits of each N-NARY number has a value of one and all of the remaining bits of the N-NARY number have a value of zero, and such that the one of the bits of each N-NARY number having a value of one is within the range of bits defined by the corresponding encoding instance selector. The set of encoding instance selectors may define a test point within a circuit under test, and may be produced by an on-chip ROM.
Additionally, the present invention comprises a number transformer that produces n-bit binary numbers having a weighted ratio of ones to zeros that is selectable on the fly, where every n-bit number produced has either exactly the selected ratio of ones and zeros, or has fewer ones than the selected ratio of ones and zeros. In this embodiment, the present invention includes a clocked pseudorandom pattern generator that produces a first n-bit binary number, at least one clocked updatable device such as a ring counter that produces a second n-bit binary number having a preselected ratio of ones and zeros, a group of n multiplexers that enable the selection of one of the ring counter outputs, and a group of n AND gates that perform a bitwise boolean AND upon the PRPG output and the selected ring counter output to produce an n-bit binary number that has either the same number or fewer 1""s than the selected ring counter output. This configuration thus provides pseudorandom n-bit binary numbers that are limited by, but not defined by, the 1-to-0 weighting assigned to each ring counter. Each ring counter has n states, and is capable of accepting a preselected n-bit binary number that defines the 1-to-0 weighting of the ring counter""s outputs. Each ring counter cycles through its n states every n clock cycles by left shifting each bit left one position and shifting the MSB into the LSB each clock cycle. The weighting of 1""s to 0""s that is desired for the output number is selected on a test point by test point basis by reading a ROM entry from a ROM, where each ROM entry corresponds to a single test point and indicates the appropriate weighting of 1s and 0s desired for the stimuli to be produced for that test point. The number generator operates synchronously, so that a properly weighted n-bit binary number appropriate for test point stimulus can be produced every clock cycle.